This header file contains SSI driver low level definition to access module registers. More...
Defines | |
| #define | SPBA_CPU_SSI 0x07 |
| #define | MXC_SSI1STX0 0x00 |
| #define | MXC_SSI2STX0 0x00 |
| #define | SSI_ENABLE_SHIFT 0 |
| #define | SSI_EARLY_FRAME_SYNC_SHIFT 0 |
| #define | SSI_PRESCALER_MODULUS_SHIFT 0 |
| #define | SSI_RX_FIFO_1_COUNT_SHIFT 28 |
| #define | SSI_FRAME_SYN_RESET_SHIFT 0 |
| #define | AC97_MODE_ENABLE_SHIFT 0 |
| #define | SSI_TEST_MODE_SHIFT 15 |
This header file contains SSI driver low level definition to access module registers.
| #define AC97_MODE_ENABLE_SHIFT 0 |
SSI AC97 Control Register (SACNT) bit shift definitions
Referenced by ssi_ac97_mode_enable().
| #define MXC_SSI1STX0 0x00 |
SSI1 registers offset
Referenced by get_ssi_fifo_addr().
| #define MXC_SSI2STX0 0x00 |
SSI2 registers offset
Referenced by get_ssi_fifo_addr().
| #define SPBA_CPU_SSI 0x07 |
This include to define bool type, false and true definitions.
| #define SSI_EARLY_FRAME_SYNC_SHIFT 0 |
STCR & SRCR Registers bit shift definitions
Referenced by ssi_rx_early_frame_sync(), and ssi_tx_early_frame_sync().
| #define SSI_ENABLE_SHIFT 0 |
SCR Register bit shift definitions
Referenced by ssi_enable().
| #define SSI_FRAME_SYN_RESET_SHIFT 0 |
SSI Option Register (SOR) bit shift definitions
| #define SSI_PRESCALER_MODULUS_SHIFT 0 |
STCCR & SRCCR Registers bit shift definitions
Referenced by ssi_rx_prescaler_modulus(), and ssi_tx_prescaler_modulus().
| #define SSI_RX_FIFO_1_COUNT_SHIFT 28 |
SFCSR Register bit shift definitions
Referenced by ssi_rx_fifo_counter().
| #define SSI_TEST_MODE_SHIFT 15 |
SSI Test Register (STR) bit shift definitions
| © Freescale Semiconductor, Inc., 2007.
All rights reserved. Freescale Confidential Proprietary NDA Required |
|