Defines | |
#define | RNGA_CONTROL_ZEROS_MASK 0x0fffffe0 |
#define | RNGA_CONTROL_RNG_TYPE_MASK 0xf0000000 |
#define | RNGA_CONTROL_RNG_TYPE_SHIFT 28 |
#define | RNGA_CONTROL_SLEEP 0x00000010 |
#define | RNGA_CONTROL_CLEAR_INTERRUPT 0x00000008 |
#define | RNGA_CONTROL_MASK_INTERRUPTS 0x00000004 |
#define | RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 |
#define | RNGA_CONTROL_GO 0x00000001 |
#define RNGA_CONTROL_CLEAR_INTERRUPT 0x00000008 |
Clear interrupt & status
#define RNGA_CONTROL_GO 0x00000001 |
Load data into FIFO
#define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 |
Enter into Secure Mode. Notify SCC of security violation should FIFO underflow occur.
#define RNGA_CONTROL_MASK_INTERRUPTS 0x00000004 |
Mask interrupt generation
#define RNGA_CONTROL_RNG_TYPE_MASK 0xf0000000 |
'RNG type' - should be 0 for RNGA
#define RNGA_CONTROL_RNG_TYPE_SHIFT 28 |
Number of bits to shift the type to get it to LSB
#define RNGA_CONTROL_SLEEP 0x00000010 |
Put RNG to sleep
#define RNGA_CONTROL_ZEROS_MASK 0x0fffffe0 |
These bits are unimplemented or reserved
© Freescale Semiconductor, Inc., 2007.
All rights reserved. Freescale Confidential Proprietary NDA Required |
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