Defines | |
#define | RNGC_CONTROL_ZEROS_MASK 0xfffffc8c |
#define | RNGC_CONTROL_CTL_ACC 0x00000200 |
#define | RNGC_CONTROL_VERIF_MODE 0x00000100 |
#define | RNGC_CONTROL_MASK_ERROR 0x00000040 |
#define | RNGC_CONTROL_MASK_DONE 0x00000020 |
#define | RNGC_CONTROL_AUTO_SEED 0x00000010 |
#define | RNGC_CONTROL_FIFO_UFLOW_MASK 0x00000003 |
#define | RNGC_CONTROL_FIFO_UFLOW_SHIFT 0 |
#define | RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR 0 |
#define | RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR2 1 |
#define | RNGC_CONTROL_FIFO_UFLOW_BUS_XFR 2 |
#define | RNGC_CONTROL_FIFO_UFLOW_ZEROS_INTR 3 |
#define RNGC_CONTROL_AUTO_SEED 0x00000010 |
Allow RNGC to generate a new seed whenever it is needed.
#define RNGC_CONTROL_CTL_ACC 0x00000200 |
Allow access to verification registers.
#define RNGC_CONTROL_FIFO_UFLOW_BUS_XFR 2 |
FIFO Underflow should cause ...
#define RNGC_CONTROL_FIFO_UFLOW_MASK 0x00000003 |
Set FIFO Underflow Response.
#define RNGC_CONTROL_FIFO_UFLOW_SHIFT 0 |
Shift value to make FIFO Underflow Response be LSB.
#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR 0 |
FIFO Underflow should cause ...
#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR2 1 |
FIFO Underflow should cause ...
#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_INTR 3 |
FIFO Underflow should cause ...
#define RNGC_CONTROL_MASK_DONE 0x00000020 |
Prevent RNGB/RNGC from generating interrupts after Seed Done or Self Test Mode completion.
#define RNGC_CONTROL_MASK_ERROR 0x00000040 |
Prevent RNGC from generating interrupts caused by errors.
#define RNGC_CONTROL_VERIF_MODE 0x00000100 |
Put RNGC into deterministic verifcation mode.
#define RNGC_CONTROL_ZEROS_MASK 0xfffffc8c |
These bits are unimplemented or reserved
© Freescale Semiconductor, Inc., 2007.
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